Designing for the Martian Environment

The ultimate goal of this project is to develop a transceiver prototype at Technology Readiness Level 5 - suitable for operation in the Martian Environment.  This is being achieved through robust design practices including low-risk transceiver architectures, up-front assessment of component performance at cryogenic temperatures, selection of a space-proven radiation-hard IC process, and iterative design of RFIC chips to refine and optimize performance  In addition, extensive testing is used throughout the project.  This page shows some of the testing activities to-date (through July 2007) including:

  • Testing of an early transmitter demonstration board
  • Testing of the Fab 1 Receiver RFIC prototype circuits at the chip and board levels
  • Testing of the Fab 2 Transmitter RFIC prototype circuits
  • Testing of the Fab 3 1-Watt Power Amplifier RFIC
  • Testing of the Fab 4 Fully-integrated 100 mW transceiver RFIC
  • Development and testing of a full transceiver constructed using the Fab 1 and Fab 2 RFICs together with a Xilinx FPGA
  • Development and testing of an Evaluation Board built from the Fab4 transceiver, Fab3 1-Watt PA, and a Xilinx FPGA


Early Demonstration Board

Early "Fab 0" prototypes of  RFIC transmitter circuits and digital bit encoding circuits have been assembled into a demonstration PC board and tested from 1 kbps to 1024 Mbps.  Photos below show the PC board together with spectrum and constellation plots for BPSK and RC-BPSK modes as well as an unmodulated carrier.  Although this prototype does not include an RF power amplifier and is therefore limited to about 0dBm output, the tests provided important information used in later RFIC designs.  

Fab0TxPCB.jpg Fab0TxTesting1.jpg Fab0TxTesting2.jpg TXfix_unmodulated_PNspectrum_200kHzSpan.gif
TXfix_8kbps_spectrum.gif Fab0TxTesting4.jpg 1p2MbpsSpectrum.jpg  

This demo board has been successfully paired with a Satcom receiver to demonstrate live, over-the-air transmissions.


Fab1:  First Receiver RFIC Prototype

The first receiver circuit RFIC was completed in 2005.  Testing took place in two stages, starting with chip-level measurements of circuit blocks such as the LNA and IF amplifiers, and then proceeding to a full PCB test.  Measurements are used to verify operation and to refine subcircuit performance in subsequent fabrication runs. These photos and figures show example measurements of the LNA at the chip level from fab 1 measurements.

LNAtestSetup.jpg LNAprobingCloseup.jpg LNAprobingMicroscopeView.jpg LNAgainMeasurement0to6GHz.gif
 LNAtestSetup  LNAprobingCloseup  LNAmicroscopeView


LNAinputZinRxMode.gif LNAinputZinTxMode.gif LNAnoiseFigureHotColdTestSetup.jpg LNAnoiseFigureHotColdSpectrums.gif






Following chip-level tests, the IC is incorporated into a PC board for overall functional, performance, and temperature testing.  Photos below show the PC board together with the spectrum of the 1-bit IF ADC output sampled at 19.2 MHz.

Rcvr1chipBonded.jpg Rcvr1PCBsideView.jpg Rcvr1PCBtopViewPowered.jpg ADCoutputTesting2.jpg
 Rcvr1chipBonded  Rcvr1PCBsideView  Rcvr1PCBtopViewPowered  ADCoutputTesting2
ADCoutputTesting1.jpg ADCoutUsingScopeWithFFT.gif ADCoutUsingSpecAn.gif ADCoutputDataDemodulated.gif
 ADCoutputTesting1  ADCoutUsingScopeWithFFT  ADCoutUsingSpecAn  ADCoutputDataDemodulated


Temperatue testing was then done to assess the operation of the receiver prototype IC at temperatures from +25C (room temperature) down to -110 C (the limit of the test setup).  The animated GIF below illustrates the signal at the output of the if filter using a -100 dBm unmodulated carrier.  The IF signal remains centered within the passband throughout the temperature range and drifts downward in frequency by the predicted amount (50 kHz).  Moreover, the gain stays constant to better than 3 dB and the noise floor falls predictably due to the cryogenic cooling of the circuits.  Please see the Cryogenic Electronics page for additional information.

Note that these results are from the first RFIC prototype which has some spurious responses due to harmonics of the internal divide-reference frequency, seen in figure at 100 kHz offset, and higher than targeted overall system noise figure due to insufficient LNA gain.  Both problems have been corrected in the Fab-2 RFIC prototype circuits tested in Spring/Summer of 2006.  

LowTempTesting1.jpg LowTempTesting2.jpg LowTempTesting3.jpg
 LowTempTesting1  LowTempTesting2  LowTempTesting3
LowTempTesting4.jpg LowTempTesting5.jpg LowTempTesting6.jpg
 LowTempTesting4  LowTempTesting5  LowTempTesting6




Fab2:  First Transmitter RFIC Prototype

The first full transmitter circuit RFIC was completed in early 2006.  The chip contains fully-integrated 10 mW and 100 mW power amplifiers in addition to a refined frequency synthesizer providing fractional-N division for fine tuning steps.  Also included are a re-spin of the receiver LNA, a mixer to allow assessment of noise from the synthesizer into the LNA/RX circuitry, and various test structures for assessment of individual blocks and components such as spiral inductors.  Example test results are illustrated below:

Fab2DiePhoto.jpg Fab2LNArespinProbing.jpg Fab2LNArespinGainMeasurement.gif Fab2IFoutWith-120dBmInputAndFracN.gif
 Die Photo  Fab 2 LNA Probing  LNAgain0to6GHz  IFout With FracN Active
Fab2PCBSideView.jpg Fab2PhaseNoiseSpectrum.gif Fab2FracNspursWith4p8MHzRef.gif Fab2BPSK1kbps100mWconstellation.jpg
 Transmitter Test PCB  Transmitter CW Spectrum  Synth Spurs With FracN  1 kbps BPSK Constellation
Fab2RCBPSK10mWconstellation.jpg Fab2100mWharmonicSpectrum.gif Fab2LNArespinNoiseWith15dB_ENR.gif Fab2_100mWoutputZ_inRxMode.gif
 RC-BPSK Constellation  TX Harmonic Levels Thru 8 GHz  LNA Hot/Cold Noise Test  100 mW PA output Z in RX mode


Fab3:  1-Watt Power Amplifier IC

The 1-Watt power amplifier needed to provide higher data return rates from the microtransciever was also tested in 2006.  Sample photos and measurement data are shown below.  Additional details will be provided following publication of results in early 2007:

1WtestSetup.jpg 1W_PAoutput.jpg PA1WharmonicLevels.gif 1W_PA_freq_response.gif
 1W PA Test Setup  1W PA Measurement  Harmonic Spectrum  Frequency Response


Fab4:  Fully-integrated Transceiver

Based on the Fab1 and Fab2 designs, a full transceiver prototype was implemented in the Fab 4 run.  All essential functions of the IC have been successfully tested so that this chip can serve as the final prototype for the project.  A set of "minor bugs" has been documented and can be used in future development projects required to bring the RFIC to a flight-ready status.  Despite these minor bugs, the Fab4 design is fully operational and usable for proof-of-concept TRL-4/5 demonstrations.

SingleChipMicrotransceiver.jpg ProbingVCOpwrAndDivNout.jpg MPAoutWideLoopBW.png MPAoutputHarmonics.png



 MPAoutWideLoopBW  MPAoutputHarmonics
FSKusingAnalogIQinputsTestSetup.jpg IFfiltOutwithTXconnectedAt-110dBmRFin.png    





Early System-Level Testing

To provide full testing of the micro-transceiver, a demonstration board was developed using the Fab 1 receiver RFIC, the Fab 2 transmitter RFIC, and a commerical FPGA for the digital modem circuits.  Interfaces include an SMA antenna connector, a JTAG programming connector, and CMOS-level I/O headers for connection to test equipment.  Preliminary testing shows that the RFICs and FPGA are functional.  The photos below show the board, together with receiver testing using -100 dBm RF inputs.  Performance testing using this board is currently on-going and is expected to be completed in the first quarter of 2007.  When the Fab 4 Transceiver chip is complete and tested, this demo board will be revised to a single-chip RFIC (plus optional 1W PA chip) design and receiver sensitivity is expected to improve by approximately 10 dB:





 Microtransceiver Demo board

 Microtransceiver Demo Board

 IF Filter Output with -100 dBm RF

 1bit Oversampled ADC Output's Spectrum


Full-Transceiver Evaluation Board Development

The final deliverable from this project is an "Evaluation Board" that is used for system-level testing with Mars infrastructure asset engineering models, and for use by Mission Planners considering the microtransceiver for future Scout development work.  The board was successfully designed and constructed in mid-2007 and is currently being used to refine the RFIC operation and to test the digital modem code using an on-board Xilinx FPGA.  It is expected to be fully operational in late 2007.

EvalBoardPhoto_m.jpg EvalBoardPhotoRFICsection_m.jpg MPAoutputWith10OhmSeriesRuncorrected_resize.jpg BPSKspectrum_resize.jpg





EvalBrdTXconstellation38kbps.jpg EvalBrdTXdemodulatedBPSKat38kbps.jpg EvalBrdRX430r7at-120dBmIFpassband.gif EvalBrdRX430r7at-120dBmADCoutTo4MHz.gif



 EvalBrdRX430r7at-120dBmIFpassband  EvalBrdRX430r7at-120dBmADCoutTo4MHz


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